This patent application is based upon and claims the benefit of the earlier filing date of Japanese Patent Application No. 2001-266264 filed Sep. 3, 2001, the entire contents of which are incorporated herein by reference.
The present invention relates to fabrication of semiconductor devices. In particular, it relates to a semiconductor device fabrication method and wafer structure, in which low-k (low dielectric constant) films are used as interlevel dielectrics in a multilayered structure.
Along with increasingly high integration and miniaturization of integrated circuits, low dielectric constant (low-k) films have come to be used as interlevel dielectrics in attempt to decrease parasitic capacitance between interconnects. In particular, in generations after the 0.25 xcexcm design rule, demand has grown for a material with reduced specific dielectric constant k that is smaller than 3 (k less than 3), from the standpoint of improving device operation speed.
Conventionally, interlevel dielectrics with a k value of approximately 4 to 5 are used, which are formed for example using chemical vapor deposition (CVD). CVD process allows the density of the interlevel dielectric film to be relatively high, and therefore, air permeability is low. Accordingly, undesirable increase in dielectric constant of multilevel dielectrics can be prevented simply by forming a passivation layer with a low permeability (e.g., SiN layer) after all of the multi-level interconnects have been formed.
However, a low-k film having a small k value generally has a low film density, and is thus vulnerable to the effects of the atmosphere. When the k value is less than 3 (k less than 3), it becomes easier for the air to penetrate into the film. If the film absorbs moisture within the air that has penetrated, the normally low dielectric constant of the film is undermined. Accordingly, with a multilayered structure using low-k films 103 and 105 such as shown in FIG. 1A, it is necessary to perform degassing for each low-k film, and thereafter, cover the low-k film 103 with air blocking protection film 104 to shut out the air.
Even if the top surface of each low-k film is covered with an air blocking protection film, the side faces of the low-k films 103, 105 along the outer circumference of the wafer are exposed if not enough care is given to the edge portion of the wafer 101. In general, edge-cut process is carried out for the purpose of preventing dust from being produced due to undesirable contact between the wafer carrier (or the wafer cassette) and the films such as photoresist films or insulating films formed over the wafer edge. Accordingly, the edges of the low-k films and the air blocking protection films are cut off at the position indicated by the arrow xe2x80x9caxe2x80x9d along the outer circumference of the wafer 101, as illustrated in FIG. 1B. In this case, if care is not taken with the sides of the low-k films 103, 105, and 109, the specific dielectric constant escalates due to the penetration of the air from the sidewalls.
Therefore, in recent years, it has been proposed to set the respective edge-cut positions for the low-k films progressively further out for each subsequently higher film, as shown in FIGS. 2A and 2B. More specifically, as shown in FIG. 2A, the edge of first low-k film 103 is cut at position xe2x80x9caxe2x80x9d, and the top surface and sidewall thereof are covered with the air blocking film 104. Second low-k film 105 is then formed over the wafer 101 and the air blocking film 104, and the edge thereof is cut at position axe2x80x2 located outside the air blocking protection film 104. Then, as shown in FIG. 2B, second air blocking film 107 is formed covering the upper surface and sidewall of the second low-k film 105. Third low-k film 109 is formed over the second air blocking film 107, and the edge-cut position is set at position axe2x80x3 yet further outward. In FIGS. 2A and 2B, arrow xe2x80x9cbxe2x80x9d indicates the edge-cut position of the photoresist used when forming interconnects 102 and interlevel interconnects 106.
In this manner, by extending the layered structure towards the outside while covering the upper surface and sidewalls of each subsequent low-k film with an air blocking protection film, it is possible to prevent penetration of the air. However, considering the fact that semiconductor devices are becoming increasingly multilayered, the edge-cut position of the first low-k film must be set inward into the wafer. If the edge-cut position is set inward, the available area for chips (i.e., the effective chip area) becomes smaller. Reduction of the effective chip area becomes more noticeable as the number of layers deposited increases. With existing techniques, since the edge-cut position is spaced approximately 0.5 mm outward for each subsequent layer, in the case of fabricating a chip with ten layers, the edge (circumference) of the first low-k film must be set at least 5 mm inside the regular edge position.
In addition, as the edge-cut position of the respective low-k films extends outward, it also becomes necessary to shift the edge-cut position of the respective resists used in the photo exposure process (PEP) for patterning interconnects 102 and 106 outward. If the edge-cut position axe2x80x3 of the upper low-k film 109 is further outward than the edge-cut position xe2x80x9cbxe2x80x9d, the periphery of the air blocking protection film 110 is etched at position b during PEP, in which the resist (not shown) deposited on the air blocking film 110 is delineated into an interconnect mask pattern. In this case, the side of the low-k film 109 is left exposed.
In general, edge cut position b of a resist during PEP is fixed, because moving the PEP edge-cut position outward for each layer would affect the mask design and mask fabrication process, causing complications in the entire manufacture processes of semiconductor devices. It has been desired, in a case of using a low-k film of k less than 3 as interlevel dielectric, to maintain a sufficiently low dielectric constant using a simple technique, without reducing the effective area of the chip taking the PEP.
In the first aspect of the invention, a semiconductor device fabrication method is provided. With this method,
(a) a first low dielectric constant film having a specific dielectric constant of k less than 3 (k less than 3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer;
(b) a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position; and
(c) a second low dielectric constant film having a specific dielectric constant of k less than 3 (k less than 3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.
In the second aspect of the invention, a semiconductor device fabrication method is provide, which comprises:
(a) forming a first low dielectric constant film having a specific dielectric constant of k less than 3 (k less than 3) over a wafer;
(b) cutting an edge of the first low dielectric constant film at a first edge cut position along the circumference of the wafer;
(c) covering the first low dielectric constant film and the wafer with a first protection film having a gas permeability lower than that of the first low dielectric constant film;
(d) cutting an edge of the first protection film at a second edge cut position that is located outside the first edge cut position;
(e) forming a second low dielectric constant film having a specific dielectric constant of k less than 3 (k less than 3) over the first protection layer; and
(f) cutting an edge of the second low dielectric constant film at the first edge cut position.
In the third aspect of the present invention, a wafer structure is provided. This wafer structure includes a wafer; a first low dielectric constant film placed over the wafer, with an edge thereof located at a first position along the circumference of the wafer; a first protection film positioned over the first low dielectric constant film, with an edge thereof located at a second position which is located outside the first position; and a second low dielectric constant film placed over the first protection layer, with an edge thereof located at the first position.
In the fourth aspect of the invention, a wafer structure includes (a) a wafer; (b) a plurality of low dielectric constant films deposited over the wafer, each dielectric constant film having an edge position, and at least two of the edge positions of the low dielectric constant films being approximately aligned with one another; and (c) an air blocking protection film covering each of the low dielectric constant films with an edge thereof positioned at a substantially fixed position located outside the edge position of the corresponding low dielectric constant film.